Conventionally, a complementary MOS (CMOS) solid-state imaging device which is already in practical use reads charge that is accumulated in a photodiode included in each pixel through an amplifying circuit including a metal oxide semiconductor (MOS) transistor.
The CMOS solid-state imaging device can be driven with low voltage and low power consumption, and is particularly used as an image input device for a cellular phone. Furthermore, in recent years, the CMOS solid-state imaging device has been incorporated in a monitoring camera and an in-vehicle camera.
A general dynamic range (a ratio between maximum intensity and minimum intensity of incident light to which an output is responsive) of the CMOS solid-state imaging device is approximately 60 dB to 80 dB, and it is expected to expand the dynamic range to approximately 100 dB to 120 dB which is comparable to a naked human eye or silver salt film. Particularly, it is further expected to expand the dynamic range when using the CMOS solid-state imaging device in the in-vehicle camera, the monitoring camera, or the like which requires capturing a recognizable image of an entire object having brightness significantly different from portion to portion.
To meet this demand, there are some known techniques of expanding the dynamic range by accumulating, in a large-volume capacitor, the charge generated in a light-receiving element (for example, see Patent Literature 1 and Patent Literature 2).
FIG. 1 is a circuit diagram showing a pixel circuit of a solid-state imaging device disclosed in Patent Literature 1.
The pixel circuit shown in FIG. 1 includes: a photodiode PD; a parasitic capacitor of a photodiode PD, or a capacitor C1 that is intentionally formed; a reset transistor M1; a transfer switch M2; a selection switch M4; a source follower transistor M6; a capacitor C2 which is a gate-source capacitor of the source follower transistor M6; a transfer switch M3; a selection switch M5; a source follower transistor M7; and a capacitor C3 which is a gate-source capacitor of the source follower transistor M7.
This configuration allows the charge accumulated in the photodiode PD and the capacitor C1 to be output via two paths: a first path via the source follower transistor M6 and a second path via the source follower transistor M7.
The pixel circuit shown in FIG. 1 can expand the dynamic range as follows.
First, the charge accumulated in the photodiode PD and the capacitor C1 is discharged to a supply of reset voltage VR via the reset transistor M1.
During a charge accumulation period, the charge generated by incident light on the photodiode PD is accumulated in the photodiode PD and the capacitor C1.
When turning on the transfer switch M2 and the transfer switch M3, the voltage of each of the capacitor C2 and the capacitor C3 varies according to the amount of charge accumulated in the photodiode PD and the capacitor C1.
Assuming, as an example, a gate size of the source follower transistor M6 as W=1 μm, L=1 μm, and a gate size of the source follower transistor M7 as W=10 μm, L=10 μm, the gate-source capacitance of the source follower transistor M7 is ten times larger than the gate-source capacitance of the source follower transistor M6. Accordingly, the capacitance of the capacitor C3 is ten times larger than the capacitance of the capacitor C2.
Accordingly, turning on the transfer switch M3 expands the dynamic range by ten times compared to the case of turning on the transfer switch M2.
FIG. 2 is a circuit diagram showing a pixel circuit of a solid-state imaging device disclosed in Patent Literature 2.
The pixel circuit shown in FIG. 2 includes: a photoelectric conversion unit (hereinafter, described as a PD unit) 371; a transfer transistor 372 which is provided adjacent to the PD unit 371 and transfers photocharge; a diffusion region (hereinafter described as an FD region) 373 provided in connection with the PD unit 371 via the transfer transistor 372); a first capacitor 374 and a second capacitor 375 which accumulate a charge overflowing from the PD unit 371 during a charge accumulating operation; a reset transistor 376 which is provided in connection with the first capacitor 374 and discharges the signal charge from the first capacitor 374, the second capacitor 375, and the FD region 373; a first accumulation transistor 377 provided between the FD region 373 and the first capacitor 374; a second accumulation transistor 378 provided between the first capacitor 374 and the second capacitor 375; an amplifying transistor 379 which reads, as voltage fluctuation, the signal charge accumulated in the FD region 373, or the signal charge accumulated in the FD region 373 and the first capacitor 374, or the signal charge accumulated in the FD region 373, the first capacitor 374, and the second capacitor 375; and a selection transistor 380 which is provided in connection with the amplifying transistor 379 and selects the pixel or a pixel block including the pixel.
The pixel circuit shown in FIG. 2 can expand dynamic range as follows.
First, prior to charge accumulation, the first accumulation transistor 377 and the second accumulation transistor 378 are turned on, and the transfer transistor 372 and the reset transistor 376 are turned off. Subsequently, with the reset transistor 376 and the transfer transistor 372 held in an On-state, the FD region 373 and the first and second capacitors 374 and 375 are reset.
Subsequently, a first noise charge N1, which is introduced into the FD region 373, the first capacitor 374, and the second capacitor 375 after turning off the reset transistor 376, is read out. In the reading, the first noise charge N1 includes a fixed pattern noise component derived from a threshold voltage of the amplifying transistor 379.
Subsequently, with the second accumulation transistor 378 held in an Off-state, the signal charge accumulated in the FD region 373, the first capacitor 374, and the second capacitor 375 is distributed according to a capacitance ratio between the FD region 373, the first capacitor 374, and the second capacitor 375.
Of the distributed charges, a second noise charge N2, which is distributed to the FD region 373 and the first capacitor 374, is read out. In the reading, the second noise charge N2 also includes a fixed-pattern noise component derived from the threshold voltage of the amplifying transistor 379.
Subsequently, during the charge accumulation period, with the first accumulation transistor 377 held in the On-state and the second accumulation transistor 378, the reset transistor 376, and the selection transistor 380 held in the Off-state, the charge is accumulated in the PD unit 371, and an excess amount of the generated charge which exceeds a maximum charge accumulation amount of the PD unit 371 is added to the noise charge N2 and accumulated in the FD region 373 and the first capacitor 374, via the transfer transistor 372 and the first accumulation transistor 377.
Furthermore, the charge exceeding the maximum charge accumulation amount of the PD unit 371 and the first capacitor 374 is accumulated in the second capacitor 375 via the second accumulation transistor 378.
This operation allows the charge overflowing from the PD unit 371 to be accumulated in another capacitor, so that the dynamic range is expanded.
Subsequently, after completion of the charge accumulation period, with the selection transistor 380 held in the On-state and the first accumulation transistor 377 held in the Off-state, the charge accumulated in the FD region 373 and the first capacitor 374 is distributed according to the capacitance ratio between the FD region 373 and the first capacitor 374.
Subsequently, a signal charge N3 distributed to the FD region 373 is read out. In the reading, the signal charge N3 also includes a fixed pattern noise component derived from the threshold voltage of the amplifying transistor 379.
Subsequently, with the transfer transistor 372 held in the On-state, the charge accumulated in the PD unit 371 is transferred to the FD region 373, and a signal charge S1 in the FD region 373 is added to the signal charge N3, to be read out.
Subsequently, with the first accumulation transistor 377 held in the On-state, the signal charge S1 in the FD region 373 and the signal charge S2 in the first capacitor 374 are mixed to be read out. Subsequently, with the second accumulation transistor 378 held in the On-state, the signal charge S1 in the FD region 373, the signal charge S2 in the first capacitor 374, and the signal charge S3 in the second capacitor 375 are mixed to be read out.
Subsequently, with the reset transistor 376 held in the Off-state, the FD region 373, the first capacitor 374, and the second capacitor 375 are reset.
A solid-state imaging device as disclosed in Patent Literature 2 expands dynamic range using a pixel circuit which keeps a high aperture ratio, by detecting the signal charge from each pixel by repeating the operation described above.